1. Technical Field
Various embodiments generally relate to a semiconductor integrated circuit.
2. Related Art
A semiconductor integrated circuit may have a single chip package structure or a multi-chip package structure including a plurality of semiconductor chips to improve the integration degree.
Examples of the multi-chip package may include a structure in which a plurality of semiconductor chips are stacked in a vertical direction so as to transmit/receive signals through a through-silicon via (TSV).
FIG. 1 is a plan view of a conventional semiconductor integrated circuit 1.
A plurality of semiconductor integrated circuits 1 illustrated in FIG. 1 may be stacked to implement a semiconductor integrated circuit having a multi-chip package structure.
Referring to FIG. 1, the conventional semiconductor integrated circuit 1 includes a plurality of memory banks BK0 to BK3, a plurality of global input/output lines GIO_L, GIO_R, WGIO, and RGIO, a unit input/output circuit block (IOCELL) 10, an input/output multiplexer (MX) 20, a buffer (BUF) 30, a latch (LAT) 40, and interface logics 50 to 70.
The interface logics 50 to 70 are configured to transmit and receive write data, read data, and command/address signals CMD/ADD to and from semiconductor chips at different layers.
Each of the interface logics 50 to 70 includes a transmitter TX, a TSV, and a receiver TX.
The unit input/output circuit block 10 performs an operation of inputting and outputting data to and from a memory bank BK0 or BK1 through a connection operation with the input/output multiplexer 20.
The buffer 30 is configured to receive and buffer the command CMD and output the buffered signal to the latch 40.
The latch 40 is configured to adjust setup/hold timing of the command CMD and output the adjusted command.
The conventional semiconductor integrated circuit 1 includes the above-described interface logics 50 to 70 so as to be used as the multi-chip package structure.
Therefore, as loading is increased by the interface logics 50 to 70, signals passing through the interface logics 50 to 70 are inevitably delayed.
Due to the above-described signal delay, the conventional semiconductor integrated circuit 1 fabricated for a multi-chip package cannot be used as a single chip package structure.
When semiconductor integrated circuits used in the single chip package structure and the multi-chip package structure, respectively, are fabricated with different structures, more serious problems than the degradation of signal characteristic may occur. For example, cost increase and productivity reduction may occur.